Modern electronic circuit design such as system-on-chip (SoC) devices or integrated circuit designs have been used in a wide range of systems, ranging from mobile computing devices to automotive control systems. These modern electronic circuit designs often present complex system issues that may be difficult and time consuming to identify and resolve, even for experienced design verification engineers. These issues include verifying whether one or more subsystems of an electronic circuit design operate as designed as well as stressing subsystem interfaces to fully characterize and verify transaction flows between multiple subsystems. While verification tools have improved, current verification methods still require significant expertise and experience to prove or disprove a property efficiently and effectively. In some cases, the slow convergence in conventional verification processes of electronic circuit designs often delays or impedes the identification and hence debug or fix of verification bottlenecks.
Moreover, SoC architectures are usually susceptible to system-level deadlocks due to layering of different interconnects and integration of pre-existing intellectual property (IP) blocks. A dead-lock free architecture or protocol of an individual IP block does not necessarily imply a deadlock-free implementation of the SoC at the system level including individual IP blocks, discrete components, and interconnections therefor. Corner case behaviors in these SoC designs as well other complex electronic circuit designs are extremely difficult to detect at the system level with conventional verification approaches.
Therefore, there is a need to improve the performance, efficiencies, and effectiveness of conventional verification techniques.